RISC-V CPU & C90 Compiler

RISC-V CPU Architecture
CPU Pipeline Diagram
Compiler AST
Code Generation

PROJECT SUMMARY COMING SOON!

Currently waiting for project to be marked before making this open source.

CPU Features

  • 5-stage pipeline (Fetch, Decode, Execute, Memory, Writeback)
  • Full RV32I instruction set implementation
  • Data hazard detection and forwarding
  • Branch prediction unit
  • Cache memory system

C90 Compiler Overview

Developed a complete C90 compiler that generates RISC-V assembly code, creating a full stack solution from high-level C code to executable machine code. The compiler implements sophisticated optimization techniques and generates efficient code for the custom RISC-V CPU.

Compiler Features

  • Full C90 standard compliance

Technologies Used

  • SystemVerilog for CPU implementation
  • C++ for compiler development